1. Field of the Invention
This invention relates to a semiconductor device, and more specifically, to a semiconductor storage device including a plurality of memory cells.
2. Description of the Related Art
A semiconductor storage device such as a dynamic random access memory (DRAM) includes a plurality of memory cells arranged so as to correspond to intersections between a plurality of word lines and a plurality of bit lines. The memory cells may be accessed for each row by selectively activating one corresponding word line. Further, an access for each memory cell may be controlled by a combination of a word line and a bit line.
However, as a result of a progress in reducing the size and increasing the integration of semiconductor devices, a potential change in each word line now affects other surrounding word lines. In other words, due to the parasitic capacitance and other such effects, when a word line is selectively activated, momentary electric potential change to other word lines now occurs. As a result, there now occurs a phenomenon that electric charges held in a memory cell connected to a different word line than the activated word line flow out to a bit line. Such outflow of the electric charges may cause loss of data written in the memory cell. Therefore, there has conventionally been conducted an electrical test called “disturb test” for examining whether such outflow of electric charges is equal to or less than a permissible value.
The disturb test involves performing an operation of sequentially selecting a plurality of word lines or an operation of repetitively selecting one or a plurality of word lines. A related semiconductor storage device is configured so that, in order to perform such operation of selecting the word lines at high speed, an internal row address strobe (RAS) signal φRAS is generated in synchronization with a clock signal generated in an internal period setting circuit, and so that a RAS-system control circuit is operated in accordance with the internal RAS signal φRAS. Examples of such semiconductor storage device include a semiconductor storage device described in Japanese Unexamined Patent Application Publication (JP-A) No. 8-227598.